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19-2257; Rev 0; 12/01
MAX3892 Evaluation Kit
General Description
The MAX3892 evaluation kit (EV kit) is an assembled surface-mount demonstration board that provides easy evaluation of the MAX3892 2.7Gbps 4:1 serializer with clock synthesis and low-voltage differential signal (LVDS) inputs. o 3.3V Single Supply o Selectable Reference Clock Frequencies: 622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz 666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz o Selectable Parallel Input Clock Rate: 622.08MHz/311.04MHz, 666.51MHz/333.26MHz o Fully Assembled and Tested Surface-Mount Board
Features
Evaluates: MAX3892
Ordering Information
PART MAX3892EVKIT TEMP RANGE -40C to +85C IC PACKAGE 44 QFN
Component List
DESIGNATION C1-C8, C10, C21, C23-C31 C9, C22 C11-C20 D1, D2 J1-J6 J7, J8, J21, J26 J9-J20, J22, J23 J24, J25 JU1, JU2, JU3, JU11, JU12, JU17, JU21, JU25, JU29, JU33, JU37, JU41, JU45, JU56 QTY 19 2 10 2 6 DESCRIPTION 0.1F 10%, 10V ceramic capacitors (0402) 10F 10%, 10V tantalum capacitors Short Red LEDs T1 SMA connectors, edge-mount, tab center EFJohnson 142-0701-851 Test points SMB connectors, PC mount EFJohnson 131-1701-201 SMA connectors, PC mount EFJohnson 142-0701-201 JU11, JU12, JU17, JU21, JU25, JU29, JU33, JU37, JU41, JU45 L1, L2, L3 R1-R6 14 1 x 3-pin headers, 0.1in centers Digi-Key S1012-36-ND R7, R8 R10, R57 R11, R18, R20, R21, R24, R25, R26, R28, R29, R42 1 x 1-pin headers, 0.1in centers Digi-Key S1012-36-ND DESIGNATION JU1, JU2, JU4, JU8, JU13, JU17, JU21, JU25, JU29, JU33, JU37, JU41, JU45, JU53, JU56 JU4, JU8, JU9, JU10, JU13, JU53, JU54, JU55 QTY DESCRIPTION
15
Shunts
8
1 x 2-pin headers, 0.1in centers Digi-Key S1012-36-ND
4 14 2
10
0 0 2 2
DO NOT INSTALL DO NOT INSTALL 768 1% resistors (0402) 30k 5% resistors (0402)
10
2k 1% resistors (0402)
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MAX3892 Evaluation Kit Evaluates: MAX3892
Component List (continued)
DESIGNATION R12-R17, R19, R22, R23, R27 R54, R56 R55 U1 U2 None None None QTY 10 2 1 1 1 1 1 1 DESCRIPTION 0 1% resistors (0402) 100 5% resistors (0402) 165 1% resistor (0402) MAX3892EGH 44-pin QFN MAX4429ESA 8-pin SO MAX3892 evaluation circuit board, rev A MAX3892 EV kit data sheet MAX3892 data sheet
not more than 2400mV P-P differential to PCLKI. Adjust the data delay from the BERT to meet the setup and hold requirement. 6) Set jumper JU1 to ground the SLBPD pin. This powers down the loopback output buffer. Loopback output at the SLBO pins can be a 622MHz clock or 2.5Gbps data, depending on the state of JU2 (SLBEN). Set SLBEN to VCC for data and GND for clock output. 7) To automatically reset FIFOERROR, install JU4. This connects the FIFOERROR pin to RESET and resets the FIFO if the FIFO buffers' elasticity is exceeded. Leave jumper JU3 open. 8) For static data inputs, install jumper JU13 to allow setting a logic state. Set up a data pattern using jumpers JU17, JU21, JU25, JU29, JU33, JU37, JU41, and JU45. Connect data line PDI- to the opposite state of PDI+. If an external data pattern is to be applied, remove the respective jumpers for the data channel. The EV kit is shipped with the data lines DC-coupled to the SMA connectors, so the instantaneous input levels must be kept between 0V and 2.4V. 9) Connect the SDO and SCLK lines at J1 through J4 to a 50 terminated oscilloscope. Use matched cable lengths when making timing measurements. 10) Power up the EV kit with a 3.3V supply. Power to J21 is required only if AC-coupling capacitors C11-C20 are installed. To install C11-C20, cut the shorting strap first. The common-mode voltage at J21 is used when the external data inputs need a level shift to be LVDS-compatible.
Component Suppliers
SUPPLIER AVX Murata Venkel PHONE 843-444-2863 415-964-6321 800-950-8365 FAX 843-626-3123 415-964-8165 512-794-0087
Note: Please indicate that you are using the MAX3892 when contacting these component suppliers.
Quick Start
1) Set jumper JU56 to the ground position for the standard SONET 2.5Gbps data rate. Alternatively, this jumper may set the RATESET pin to VCC for an FEC 2.7Gbps data rate. 2) Install JU53 for a 622MHz reference clock at the RCLK pins. See Figure 1 for other reference clock frequencies. Install no jumper or install only one of jumpers JU53, JU54, or JU55, based on the reference clock frequency. 3) Apply a 622MHz clock to the RCLK inputs at J24 and J25. The LVPECL input voltage should be at least 300mV P-P differential, but not more than 1900mVP-P differential. 4) Install JU8 to select a 622MHz clock input to PCLKI for latching in the parallel data. This also enables the SCLKO for retiming the 2.5Gbps serial data. See Figure 1 for other states of the MODE pin. Install none or one of jumpers JU8, JU9, or JU10. 5) Connect PCLKO lines at J22 and J23 to PCLKI inputs at J12 and J11 (PCLKO+ is connected to PCLKI-). Alternatively, apply a 622MHz clock with LVDS levels of at least 100mVP-P differential, but
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MAX3892 Evaluation Kit
Detailed Description
Control Descriptions (see Quick Start first)
COMPONENT J1, J2 J3, J4 J5, J6 J7 J8, J26 J9 J10 J11, J12 J13-J20 J21 J22, J23 J24, J25 JU1 JU2 JU3 JU4 JU8, JU9, JU10 JU13 JU17, JU21, JU25, JU29, JU33, JU37, JU41, JU45 JU53, JU54, JU55 JU56 NAME SCLKO SDO SLBO VCC GND RESET FIFOERROR PCLKI PDI CMV PCLKO RCLK SLBPD SLBEN RESET FIFOERROR MODE STATIC DATA PDI0 to PDI3 FUNCTION Serial Clock Output, CML, Differential 2.5GHz/2.7GHz Clock Serial Data Output, CML, Differential 2.5Gbps/2.7Gbps Data Serial Loopback/Data Output, CML, Data, or Clock Supply Voltage Supply Ground External Reset Connection, TTL Input External FIFOERROR Connection, TTL Output Parallel Clock Input, LVDS Parallel Data Input, LVDS Common-Mode Voltage. Not required for DC-coupled LVDS inputs. Set to approximately 1.2V when C11-C20 are installed. Parallel Clock Output, LVDS Reference Clock Input, LVPECL Powers down the system loopback outputs when low. Loopback outputs are enabled when high. Loopback Enable Input. SLBEN high enables serial data. SLBEN low enables a 622MHz/666MHz clock. FIFO Error Reset. Pull high to unlatch FIFOERROR output, and center the FIFO in its elastic range. FIFO Error Indicator. Connect FIFOERROR to RESET to reset the FIFO automatically. Select PCLKI Frequency 622MHz/311MHz, and Enable/Disable SCLKO. Install only one jumper or leave open. See Figure 1. Install JU13 when using the static data jumpers below. Parallel Data Input Static Level Setup. Install PDI+ to the opposite state of PDI-. Select RCLK Frequency (622MHz, 155MHz, 77MHz, 38MHz). Install one jumper or leave open. See Figure 1. SONET or FEC Data Rate Select. Set high for FEC or low for SONET.
Evaluates: MAX3892
CLKSET RATESET
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Evaluates: MAX3892
FIL
VCC
RCLK-
RCLK+
CLKSET
PCLKO-
VCCVCO
GND VCCO SCLKOSCLKO+ VCCO SDOPDI130 VCCD PDI0+ 31 PDI032
RATESET
PCLKO+
R14 0 1 GND 2 3.3V 3 4 5 C5 0.1F R3 OPEN VCCVCO 3.3V 6 J3 SDO33
J2 SCLKO+
GND
VCC
MAX3892 Evaluation Kit
FIFOERROR
SLBPD
GND
VCC
PCLKI+
RESET
MODE
PCLKI-
J5 SLBO3.3V VCCD JU1 VCCD VCCD JU2 VCCD JU3 D1 JU4 D2 VCCD J6 SLBO+ C8 0.1F R6 OPEN
SLBEN
LOL
GND
Figure 1. MAX3892 EV Kit Schematic
VCCD VCCD C28 0.1F C29 0.1F C22 10F J26 C24 0.1F C23 0.1F C30 0.1F C31 0.1F R54 100 R55 165 JU13 R57 30k JU54 VCCO JU53 JU56 VCCVCO C25 0.1F C20 SHORT J20 PDI0VCCD R21 2k JU41 R20 2k JU37 R42 2k JU33 C21 0.1F R24 2k JU29 24 PDI3PDI3+ 23 JU25 R25 2k C15 SHORT J15 PDI2+ C14 SHORT C16 SHORT J16 PDI225 C17 SHORT C18 SHORT J18 PDI1JU45 C19 SHORT J19 PDI0+ C1 0.1F C27 0.1F C26 0.1F R56 100 JU55 J25 RCLKJ24 RCLK+ J23 PCLKOJ22 PCLKO+ J21 CMV REQUIRED FOR AC-COUPLING VCCO 3.3V VCCD J1 SCLKO3.3V C4 0.1F R2 OPEN C3 0.1F R1 OPEN
4
44 43 38 42 41 39 35 40 37 36 34
3.3V
J7
L1 OPEN
C9 10F
C10 0.1F
R12 0
J8
R23 0
R13 0
L2 OPEN
R22 0
R15 0
R27 0
L3 OPEN
U1 MAX3892
GND 27 PDI2PDI2+ 26
PDI1+ 29 28 VCC
J17 PDI1+
R19 0 C6 0.1F R4 OPEN SDO+ VCCO SLBOSLBO+ VCCO 8 9 10 3.3V 11 C2 0.1F VCCD C7 0.1F R5 OPEN J4 SDO+ 7
R16 0
R17 0
12 13 14 15 16 18 17
19
20
21
22
JU21 VCCD JU8 JU9 JU17 R10 30k JU10
RATESET JU56 lo SONET hi FEC
R26 2k
J14 PDI3R28 2k C13 SHORT J13 PDI3+ C12 SHORT R29 2k J12 PCLKI-
CLKSET JU53 OPEN JU54 JU55
622.08MHz 155.52MHz 77.76MHz 38.88MHz
U2 MAX4429
6 7 J9 RESET 2 R8 768
MODE R7 768
JU8
622MHz, SCLK
JU12 R18 2k J10 FIFOERROR JU11 R11 2k C11 SHORT J11 PCLKI+
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OPEN
622MHz
JU9
311MHz
JU10
311MHz, SCLK
MAX3892 Evaluation Kit Evaluates: MAX3892
1.0"
Figure 2. MAX3892 EV Kit Component Placement Guide--Component Side
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MAX3892 Evaluation Kit Evaluates: MAX3892
1.0"
Figure 3. MAX3892 EV Kit Component Placement Guide--Solder Side
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MAX3892 Evaluation Kit Evaluates: MAX3892
1.0"
Figure 4. MAX3892 EV Kit PC Board Layout--Component Side
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MAX3892 Evaluation Kit Evaluates: MAX3892
1.0"
Figure 5. MAX3892 EV Kit PC Board Layout--Ground Plane
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MAX3892 Evaluation Kit Evaluates: MAX3892
1.0"
Figure 6. MAX3892 EV Kit PC Board Layout--Power Plane
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MAX3892 Evaluation Kit Evaluates: MAX3892
1.0"
Figure 7. MAX3892 EV Kit PC Board Layout--Solder Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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